There has been substantial interest within the industry to develop integrated circuit devices having mixed bipolar and MOS technologies. The obvious advantage is the ability to perform both analog and digital functions on the same chip thereby enhancing and expanding potential applications of a single device.
Past efforts to achieve such structures fall into two categories, both of which utilize the epitaxial layer of a silicon-on-insulator (SOI) device as the active region containing the bipolar structure. The first category is a vertically arranged bipolar transistor wherein a base region is formed part way, but not completely, through the epitaxial layer and an emitter region is formed within this base region. The remaining epitaxial material which is around and beneath the base region serves as the collector. Examples of such structures will be found in U.S. Pat. No. 3,974,560 which issued Aug. 17, 1976 to Mueller et al. and U.S. Pat. No. 4,127,860 which issued Nov. 28, 1978 to Beilitz et al. A difficulty with this type of structure is that epitaxial layers are typically very thin, about 0.5 microns, with the region nearest the substrate having numerous defects. Necessarily, the base of the collector junction is formed in this defect region resulting in poor device performance. The second category is a laterally arranged bipolar transistor wherein the collector, base, and emitter are adjacent regions each of which is formed completely through the epitaxial layer. This structure provides the full thickness of the epitaxial layer to form the PN junctions and thereby avoids the difficulty mentioned above with respect to the first category of structure.
An example of this second category structure is disclosed in U.S. Pat. No. 4,050,965, which issued Sept. 27, 1977 to Ipri et al. Ipri discloses a lateral bipolar transistor formed in an epitaxial layer. P type dopants are implanted in what will ultimately become the emitter region adjacent one side of the gate. The P type dopants are diffused under the gate, a small amount thereby forming the base region. The collector and emitter regions are then implanted with N type dopants using the gate as a mask in the usual manner. This results in an N+ collector region adjacent one side of the gate, an N region under the gate, a narrow P type base region also under the gate, and an N+ type emitter region adjacent the other side of the gate. While this type of structure yields a transistor that is superior to the first category type transistor, it is difficult to control the width of the base region because it is dependent upon both the base and emitter diffusion parameters.